The trend in radio communications systems is toward higher levels of integration to achieve performance, cost, size, and power dissipation goals. The greatest single barrier to higher integration is the undesired interaction or crosstalk that exists between circuits as more circuits are combined on fewer integrated circuits (ICs). In recent years, integration has advanced to the point that researchers have introduced the concept of a "single chip transceiver IC". In particular, communication devices such as frequency modulated (FM) portable radios, cellular phones, and packet radios would feature all of the transmit and receive functions on a single IC substrate with the programmable features and user interface functions performed by a second IC such as low-cost micro-controller unit (MCU).
This "single chip transceiver IC" programmed and controlled by an MCU has obvious implementation problems in regards to undesired circuit crosstalk with dozens if not hundreds of circuits located on the same IC substrate. For example, a state of the art communication device such as a narrow band FM transceiver can receive and demodulate an extremely low-level RF signal. The signal level may be 1 microvolt (.mu.V) or less. This same FM transceiver is commonly controlled by a MCU that has digital clock signals with amplitudes in the 2.7 to 5 V range. The digital clock signals which are routed both on-chip and off-chip, conduct and radiate higher-order harmonic signals that can interfere with the desired incoming RF signal and/or a mixed down product of the desired RF signal. The higher-order harmonics may also fall exactly at the desired RF frequency and appear to the receiver as a valid incoming signal. In this case, the FM receiver would exhibit desense known as "self-quieting" due to the undesired unmodulated signal causing the FM receiver to mute (or quiet) with no discernible audio output. The undesired signal is known as a self-quieting spur.
Receiver desense may be caused by any digital or analog signal (or harmonic thereof) but most often occurs at harmonics of the MCU's input clock signal or harmonics of the MCU's internal system clock (e.g. E clock). The self-quieting spurs most likely occur at harmonics of the MCU's clock signals, because these signals drive a large number of devices both on the MCU and on the external input/output (I/O) addressing. The switching of a large number of devices creates transient currents on the supply and ground lines. The high harmonic content of the switching transients results in the desense of receiver circuits that operate at the same frequency or a mixed down frequency that is equal to a particular MCU clock harmonic frequency. Therefore, a means to prevent the desense of the highly sensitive transceiver circuits due to the crosstalk of the digital clock signals is desired.
In the past, decoupling and shielding techniques have been used on the supply and ground lines to prevent undesired coupling of the harmonics onto the receiver circuits. However, shielding and decoupling components can be costly and also have a negative impact in terms of radio size, parts count, and ease of assembly. Shielding at the IC level is also costly and difficult to implement and requires multiple metallization layers.
Another approach to MCU desense of the receiver is to shift the frequency of the oscillator that produces the MCU's input clock signal to an alternative frequency. This approach is feasible because the MCU clock frequency and the user's assigned receiver frequencies are known values at the time of radio assembly and programming. The user typically selects the frequency from a front panel selector. Because the MCU clock frequency and the user's assigned receiver frequencies are known, a self-quieting spurious analysis is first performed prior to radio programming to determine if a harmonic of any of the MCU clocks falls within the receiver bandwidth of any of the user's assigned receiver frequencies. If an MCU harmonic frequency falls within the receiver bandwidth of an assigned receiver frequency, the radio is programmed to automatically shift the MCU crystal oscillator approximately 1000 Hz above (or below) its nominal frequency. This action moves the undesired MCU clock harmonic signal from F.sub.UNSHIFTED =N.times.F.sub.MCU to F.sub.SHIFTED =N.times.(F.sub.MCU+ 1000 Hz) where N is Nth harmonic of the MCU clock. The MCU clock frequency is offset only a small amount, such as 1000 hertz (Hz), because a greater frequency offset would cause shifts in the MCU's critical timing signals that are used to generate I/O functions such as audible and sub-audible signaling. In the event that an assigned receiver frequency is not located at or near any of the MCU harmonic frequencies, then no shift is required and the MCU oscillator operates at its nominal frequency (F.sub.MCU).
The problem with the shiftable oscillator approach is a separate crystal oscillator circuit is required to generate the MCU clock signal. It is desirable to use only one reference oscillator for the entire FM transceiver. The crystal oscillator typically used to generate the reference signal for a local oscillator (LO) synthesizer cannot be shifted due to the high frequency stability requirement (typically+/-5 ppm) for the LO signal. Therefore, the FM receiver utilizing the shiftable oscillator approach has the disadvantage of requiring two oscillator circuits--one for the MCU and one for the LO synthesizer.
Another approach to avoid MCU desense of the receiver is to generate the MCU clock signal with a frequency synthesizer that can be programmed to shift the MCU clock signal approximately 1000 Hz above or below the MCU nominal clock frequency. In this approach, a single high-stability reference oscillator may be used to generate the reference signal used by both the MCU clock synthesizer and the LO synthesizer. The decision to shift the MCU clock frequency is determined by performing a self-quieting analysis as described in the second approach. However, the MCU synthesizer circuit requires a full phase lock loop (PLL) circuit including a reference divider, phase detector, voltage controlled oscillator (VCO), programmable divider, and loop filter. The loop filter typically requires a pin-out to an off-chip capacitor, and the synthesizer requires numerous programming bits to provide sufficient resolution to synthesize small clock shifts such as 1000 Hz. The overhead in terms of pin-outs, die area, number of programming bits, and testability is high with this two synthesizer approach. In addition, the additional MCU synthesizer itself is susceptible to crosstalk from other transceiver circuits located on the same substrate.
Accordingly, there is a need for an improved apparatus and technique for minimizing the desense of a received signal caused by harmonics of the MCU clock signal and/or by other master clock signals on the transceiver. To achieve high-level integration at low-cost, the apparatus must provide a solution to the desense problem but not produce undesired shifts to critically timed circuits. The apparatus itself should be immune to crosstalk from nearby circuits and require minimum die area.